The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory element having a floating gate situated between an overlapping control gate and a channel region which is situated in the semiconductor body and extends between a source zone and a drain zone, by which method an active region of a first conductivity type adjoining the surface is defined in the semiconductor body, and a floating gate dielectric is provided, to which floating gate dielectric the floating gate is applied, the floating gate having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and having sidewall portions extending substantially perpendicularly to the surface of the semiconductor body, which floating gate is provided with an inter-gate dielectric, to which inter-gate dielectric the control gate is applied, which control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone.
A method of manufacturing a semiconductor device of the kind described in the opening paragraph is known from U.S. Pat. No. 5,395,778. In the known method, the active region of the semiconductor body is provided with a first insulating layer providing the floating gate dielectric, to which first insulating layer a silicon layer is applied from which the floating gate is formed. After formation of the floating gate, the source zone and the drain zone are provided in the semiconductor body and a second insulating layer is applied providing the inter-gate dielectric. In a next step, a conductive layer is applied from which the overlapping control gate is formed, which overlapping control gate is capacitively coupled not only to the substantially flat surface portion of the floating gate but also to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone.
A disadvantage of the known method is that, at least adjacent to the source zone and the drain zone, the overlapping control gate is insulated from the semiconductor body only by a stack of the first insulating layer providing the floating gate dielectric covered with the second insulating layer providing the inter-gate dielectric. Consequently, parasitic capacitances are induced during operation of the memory element between the overlapping control gate on the one hand and the source zone and the drain zone in the semiconductor body on the other hand, which parasitic capacitances disadvantageously increase the supply voltage of the memory element.
It is an object of the invention to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph, which method suppresses the induction of parasitic capacitances between the overlapping control gate and the semiconductor body and, hence, counteracts an increase in the supply voltage of the memory element.
According to the invention, this object is achieved in that after the definition of the active region, a patterned layer is applied, which patterned layer acts as a mask during the formation of the source zone and the drain zone of a second conductivity type in the semiconductor body, after which a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer, in which recess a first insulating layer is applied providing the floating gate dielectric of the memory element, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer, which first conductive layer is shaped into the floating gate by means of mask etching, which floating gate is covered with a second insulating layer providing the inter-gate dielectric of the memory element, to which second insulating layer a second conductive layer is applied, which second conductive layer is shaped into the overlapping control gate.
The above-stated measures in accordance with the invention enable the manufacture of a non-volatile memory element having a control gate which is capacitively coupled to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone, the overlapping control gate being insulated from the semiconductor body by a stack the thickness of which is increased by a dielectric layer having a thickness which is relatively large compared with the thicknesses of the first insulating layer providing the floating gate dielectric and the second insulating layer providing the inter-gate dielectric of the memory element. In this way, induction of parasitic capacitances between the overlapping control gate and the semiconductor body is suppressed and, hence, an increase in supply voltage is counteracted.
After the definition of the active region, a patterned layer is applied, which is used as a mask during the subsequent formation of a source zone and a drain zone. Prior to removal of the patterned layer, a relatively thick dielectric layer is applied in a thickness which is sufficiently large to cover the patterned layer. The dielectric layer is subsequently removed over part of its thickness by means of, for instance, chemical-mechanical polishing (CMP) until the patterned layer is exposed, which patterned layer is removed by means of selective etching, thereby forming a recess in the dielectric layer. After the removal of the patterned layer, a dip-etch may be carried out in order to remove a surface layer composed of, for instance, silicon oxide, which may have been advantageously applied to the surface of the semiconductor body in order to protect the semiconductor body against contamination. A first insulating layer is applied providing the floating gate of the memory element, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer. The first conductive layer is subsequently shaped into the floating gate of the memory element by means of mask etching, the floating gate having a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and sidewall portions extending substantially perpendicularly to the surface of the semiconductor body. Then, a second insulating layer is applied providing the inter-gate dielectric of the memory element, to which second insulating layer a second conductive layer is applied, which is shaped into the overlapping control gate of the memory element by means of mask etching. The overlapping control gate is capacitively coupled not only to the substantially flat surface portion of the floating gate but also to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone. An additional removal of the second insulating layer and the first insulating layer using the same mask as applied during etching of the control gate is not required, but may be beneficial in case a material with a high dielectric constant is applied for the second insulating layer and/or the first insulating layer.
In order to achieve a large capacitive coupling between the floating gate and the overlapping control gate, it is advantageous to use an oversized mask during etching of the first conductive layer into the floating gate. In that way, the conductive material of the floating gate will stretch out over the dielectric layer, which is coated with the first insulating layer, to substantially beyond the recess in the dielectric layer at least in the directions of the source zone and the drain zone.
For MOS devices with channel lengths decreasing below about 2 xcexcm, short-channel effects start to play an important role in respect of device behavior. Conventionally, impurities for suppressing short-channel effects are introduced after the definition of active regions adjoining the surface of the semiconductor body and after the application of a gate oxide layer covering the entire surface of the semiconductor body. In this way, the introduced impurities are distributed laterally over the entire active regions instead of over the channel regions only, and counter-doping is required for the subsequent formation of source and drain zones in regions adjoining the surface of the semiconductor body.
In order to counteract the necessity of counter-doping for the formation of a source zone and a drain zone, it is advantageous to locally introduce the above-mentioned impurities via the recess into the channel region of the semiconductor body in a self-registered way by using the dielectric layer as a mask.
The impurities may be introduced into the channel region of the semiconductor body by means of a diffusion process, involving two steps in general. First, the impurities are placed on or near the surface of the semiconductor body by a gaseous deposition step or by coating the surface with a layer containing the desired impurities. This is followed by an annealing treatment in order to further drive-in the impurities into the semiconductor body by means of diffusion. An alternative to the diffusion process, is ion implantation. The desired impurities are first ionized and then accelerated by an electric or magnetic field to a high energy, typically in the range from 1 to 500 keV. A beam of the accelerated high-energy ions strikes the surface of the semiconductor body and penetrates exposed regions thereof. The penetration is typically less than a micrometer below the surface, and considerable damage is done to the crystal lattice during implantation. Consequently, an annealing treatment is required in order to restore the damage to the crystal lattice and to activate the as-implanted impurities.
Due to its ability to more precisely control the number of introduced impurities into the semiconductor body, ion implantation is preferred to diffusion. Moreover, ion implantation allows impurity introduction into the semiconductor body with much less lateral distribution than obtainable via diffusion and, hence, allows devices to be manufactured with features of smaller dimensions.
As mentioned before, short-channel effects start to play an important role for MOS devices with channel lengths decreasing below about 2 xcexcm. In particular, the short-channel effects known as punchthrough and short-channel threshold-voltage shift become dominant.
Punchthrough is a phenomenon associated with the merging of the depletion regions of the source zone and the drain zone. That is, as the channel gets shorter, the edges of the depletion regions get closer, assuming that the channel-region doping is kept constant as the channel length decreases. When the channel length becomes equal to roughly the sum of the widths of the depletion regions of the source zone and the drain zone, punchthrough is established.
Experimentally, it is observed that, as the channel length decreases to less than about 2 xcexcm, the threshold voltage shifts to a value below the long-channel values, which effect is referred to as the short-channel threshold-voltage shift. The fraction of the depletion charge within the channel region under the gate, which is induced by the source zone and the drain zone, is insignificant for long-channel devices, but becomes significant for short-channel devices with the channel length approaching the sum of the widths of the depletion regions of the source zone and the drain zone. Consequently, less charge is needed to cause inversion, and the threshold voltage is reduced.
On the above grounds, it is advantageous to provide the channel region of a short-channel memory element with an impurity region for threshold voltage correction and/or punchthrough suppression. In order to reach these effects, the doping of the semiconductor body within the channel region under the floating gate needs to be increased in general. Impurities for threshold voltage correction and/or punchthrough suppression can be implanted into the channel region substantially perpendicularly to the surface of the semiconductor body. However, in order to counteract channeling of the impurities along crystal directions and planes, it is advantageous to implant the impurities into the channel region at a small angle of a few, for instance seven, degrees with the normal to the surface of the semiconductor body by tilting the semiconductor body before implantation. It is to be noted that an implantation for punchthrough suppression in general leads to an increase of the threshold voltage as well.
A further improvement of a non-volatile memory element can be achieved by a so-called halo implant, also known as pocket implant, which in general is applied in order to reach a more efficient hot-carrier generation and, hence, to increase the program speed of the memory element. For this purpose, impurities are advantageously implanted into the channel region of the memory element at an acute angle with the normal to the surface of the semiconductor body. The maximum angle at which the impurities can be implanted into the channel region is dependent on the aspect ratio of the recess in the dielectric layer.
The patterned layer, which is used as a mask during the formation of the source zone and the drain zone of the memory element, may be applied comprising, for instance, silicon nitride or aluminum oxide. However, in order to match the process flow to conventional CMOS processing, the patterned layer is advantageously applied comprising silicon. In this respect, polycrystalline silicon, or possibly amorphous silicon or GexSi(1xe2x88x92x) may be applied, with the fraction of germanium x lying in the range between 0 and 1.
Experimentally, it is observed that the moment of stopping the chemical-mechanical polishing (CMP) of the dielectric layer is rather critical if the patterned layer is composed of silicon. In case the CMP process is stopped too early, oxide residue is left on the patterned layer which hinders the subsequent removal of the patterned layer. In case the CMP process is carried on too long, the definition of the height of the floating gate, which is planned to be provided at a later stage of the process, is adversely affected. In order to improve the height definition of the process, it is preferred to apply the patterned layer as a double-layer consisting of a first sub-layer comprising the silicon and, on top thereof, a second sub-layer composed of a material having a larger resistance to the material removing treatment than silicon and being selectively etchable with respect to the dielectric layer. Hence, the second sub-layer will act as etch stop layer during the removal of the dielectric layer. In this respect it is advantageous to apply silicon nitride as the second sub-layer and silicon oxide as the dielectric layer. Alternatively, aluminum oxide can be used instead of silicon nitride and/or BPSG (borophosphosilicate glass) instead of silicon oxide.
The control gate and/or the floating gate of the non-volatile memory element and, hence, the second conductive layer and/or the first conductive layer can be advantageously applied comprising a metal instead of conventional polycrystalline silicon. In contrast with polycrystalline silicon, metals intrinsically have a relatively low resistance and do not suffer from detrimental depletion effects. In this respect a low-resistance metal such as aluminum, tungsten, copper or molybdenum can be advantageously applied. In case a metal is used, the second conductive layer and/or the first conductive layer may be advantageously applied as a double-layer consisting of a layer comprising the metal on top of a layer acting as adhesion layer and/or barrier layer. In this respect titanium (Ti) may be used as adhesion layer and titanium nitride (TiN) or titanium tungsten (TiW) as barrier layer.
In order to improve the performance of the non-volatile memory element, it may be advantageous to apply a dielectric material with a dielectric constant higher than that of silicon oxide (xcex5xcx9c4) as the inter-gate dielectric and/or the floating gate dielectric of the memory element and, hence, as the second insulating layer and/or the first insulating layer. In this respect, tantalum oxide (Ta2O5; xcex5xcx9c20-25), aluminum oxide (Al2O3; xcex5xcx9c10) or silicon nitride (Si3N4; xcex5xcx9c7) can be applied to advantage, as these materials are deposited in a conformal and reproducible way by means of chemical vapor deposition (CVD).